Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an internal voltage generation circuit of a semiconductor device.
In semiconductor devices including a DRAM, internal voltage generators are provided inside a chip to generate a plurality of internal voltages with various voltage levels by using a power supply voltage (VDD) and a ground voltage (VSS) supplied from an outside. The plurality of internal voltages are used for operations of internal circuits of the chip.
In general, processes for generating the plurality of internal voltages include a process for generating a reference voltage with a reference voltage level, and a process for generating the internal voltages through charge pumping or down converting (VDC: voltage down converting or LDO: low drop out) by using the generated reference voltage.
Among the internal voltages of the semiconductor device, a boosting voltage (VPP) and a back bias voltage (VBB) are typically generated through the charge pumping and a core voltage (VCORE) are typically generated through the down converting.
The boosting voltage (VPP) is a voltage which has a voltage level higher than the external power supply voltage (VDD). The boosting voltage (VPP) is supplied to a word line coupled to the gate of a cell transistor when a cell is accessed so as to prevent loss of cell data due to the threshold voltage (Vth) of the cell transistor.
The back bias voltage (VBB) is a voltage which has a voltage level lower than the external ground voltage (VSS). The back bias voltage (VBB) is generated to suppress the change of the threshold voltage (Vth) of the cell transistor due to a body effect on the cell transistor, thereby improving operational stability of the cell transistor and reducing channel leakage current induced in the cell transistor.
The core voltage (VCORE) is a voltage which has a voltage level lower than the external power supply voltage (VDD) and higher than the external ground voltage (VSS). The core voltage (VCORE) is generated to decrease the magnitude of power for maintaining the voltage level of the data stored in a cell and ensure stable operation of the cell transistor.
Internal voltage generators for generating the internal voltages (VPP, VBB and VCORE) are designed to operate with predetermined deviation values within operation voltage and temperature ranges of the semiconductor device.
FIG. 1 is a block diagram illustrating a conventional circuit for generating an internal voltage in a voltage down converting type in a semiconductor device.
Referring to FIG. 1, a conventional circuit for generating an internal voltage in a voltage down converting type in a semiconductor device includes an enable signal generation unit 100, a reference voltage generation unit 140 and a plurality of internal voltage generation units 120A, 120B, 120C, 121A and 121B. The enable signal generation unit 100 is configured to generate a plurality of enable signals ENABLE1 and ENABLE2 corresponding to operations of a semiconductor device based on a command COMMAND applied from an outside. The reference voltage generation unit 140 is configured to generate a reference voltage REF which maintains a constant level regardless of variations in PVT (process, voltage and temperature) of the semiconductor device. The plurality of internal voltage generation units 120A, 120B, 120C, 121A and 121B are configured to generate internal voltages VINT through down converting based on a predetermined target level corresponding to the reference voltage REF and be controlled in its on/off operation in response to the plurality of enable signals ENABLE1 and ENABLE2.
In detail, the plurality of internal voltage generation units 120A, 120B, 120C, 121A and 121B include first internal voltage detection sections 122A, 122B and 122C, second internal voltage detection sections 123A and 123B, first voltage driving sections 124A, 124B and 124C, and second voltage driving sections 125A and 125B. The first internal voltage detection sections 122A, 122B and 122C are configured to be controlled in their on/off operations in response to a first enable signal ENABLE1 among the plurality of enable signals ENABLE1 and ENABLE2. The second internal voltage detection sections 123A and 123B are configured to be controlled in their on/off operations in response to a second enable signal ENABLE2 among the plurality of enable signals ENABLE1 and ENABLE2. The first voltage driving sections 124A, 124B and 124C are configured to drive the terminals of the internal voltages VINT to a voltage level corresponding to the predetermined target level based on the reference voltage REF in response to output signals VINT_DET0, VINT_DET1 and VINT_DET2 of the first internal voltage detection sections 122A, 122B and 122C. The second voltage driving sections 125A and 125B are configured to drive the terminals of the internal voltages VINT to a voltage level corresponding to the predetermined target level based on the reference voltage REF in response to output signals VINT_DET3 and VINT_DET4 of the second internal voltage detection sections 123A and 1236.
The internal voltages VINT generated through the processes described above are inputted to an internal circuit 160 of the semiconductor device and are used to perform predetermined internal operations.
In the conventional circuit for generating an internal voltage in a voltage down converting type in a semiconductor device, the on/off operations of the plurality of internal voltage generation sections 120A, 120B, 120C, 121A and 121B are controlled by the plurality of enable signals ENABLE1 and ENABLE2 of which activation or deactivation is determined in response to the command COMMAND applied from the outside.
Accordingly, in the conventional semiconductor device, the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C which are to be provided to generate the internal voltages through down converting may be determined based on design needs. Thus, a conventional method for generating internal voltages raises the following concerns.
First, since the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C for the stable internal voltage may not be accurately predicted while a semiconductor device is designed, an increased number of internal voltage generation units 120A, 120B and 120C, 121A and 121C may be disposed in the semiconductor device in preparation for a worst case. As a consequence, the entire area of the semiconductor device may increase.
Second, in designing the semiconductor device, the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C controlled by one enable signal ENABLE1 or ENABLE2 among the plurality of enable signals ENABLE1 and ENABLE2 is to be determined. At this time, because there is no common standard that the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C should be determined based on, the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C may be determined based on the prediction a forecast made in view of such a simulation result, which may not be accurate. Due to this fact, as an increased number of internal voltage generation units 120A, 120B and 120C, 121A and 121C, which is greater than the number of internal voltage generation units for the actual operation, are controlled by one of the plurality of enable signals ENABLE1 and ENABLE2, power consumption of the semiconductor device may increase.
Also, when determining in advance the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C, since amount of current which increases due to variations in PVT (process, voltage and temperature) can be additionally considered (as a preparation for a worst case), an increased number of internal voltage generation units 120A, 120B and 120C, 121A and 121C, which is greater than the number of the internal voltage generation units for the actual operation, are to be designed to be turned on at a time. Hence, even if the number of internal voltage generation units 120A, 120B and 120C, 121A and 121C for the actual operation are disposed in the semiconductor device based on the relatively accurate simulation result, an increased amount of current which is greater by several mA to several ten mA than the amount of current to be consumed for the actual operation may be consumed, which raises a concern.
In the above-mentioned example, three internal voltage generation units 120A, 120B and 120C are on/off-controlled in response to the first enable signal ENABLE1, and two internal voltage generation units 121A and 121B are on/off-controlled in response to the second enable signal ENABLE2. A determination is made as to how to match the plurality of enable signals ENABLE1 and ENABLE2 with the plurality of internal voltage generation units 120A, 120B and 120C, 121A and 121C based on a simulation result which may not be accurate and a forecast made based on a worst case scenario. Therefore, actually, the semiconductor device may operate stably even when, for example, two internal voltage generation units 120A and 1208 are on/off-controlled in response to the first enable signal ENABLE1 and one internal voltage generation unit 121A is on/off-controlled in response to the second enable signal ENABLE2. At this time, an increased number of internal voltage generation units 120A, 120E and 120C, 121A and 121C may cause a defect in the semiconductor device.
Since it is difficult to detect the occurrence of such a defect after the semiconductor device is mounted and used, it is also difficult to prevent the occurrence of the defects.